Recently, attention has been drawn to logic circuits that can reconfigure (or reprogram) functions in accordance with user programs. For example, a field programmable logic array (FPGA) that has been developed by the LSI technique is widely used (disclosed by S. Trimberger in Proc. IEEE 81 (1993) pp. 1030-1041, S. Hauck in Proc. IEEE 86 (1998) pp. 615-638, and Toshinori Sueyoshi in “Programmable Logic Devices” IEICE Tech. Report, Vol. 101, No. 632, (2002) pp. 17-24, for example). Conventionally, the FPGA has been used only for test products and limited products. However, since shipment can be made quickly and the functions can be rewritten after shipment, the FPGA is incorporated as the last component into mobile devices such as portable telephone devices that tend to be replaced with newly developed devices in a short time. Also, studies have been made on the FPGA as an information device of novel architecture that reconfigures its hardware for each operation.
There are several types of configurations for the FPGA. Among them, the Look Up Table (LUT) method using SRAMs is most widely used. In this configuration, small-sized logic blocks that are formed with LUTs for achieving desired functions are arranged in a matrix fashion, and the blocks are connected to one another with lines that can be changed by a switch (a pass transistor, for example) (see FIG. 57A).
A desired logic circuit is realized by rewriting the values to be written in the register of the LUT and the switch for the lines. Each logic block includes a flip-flop (FF) for operations in synchronization with the LUT (see FIG. 57B). The LUT includes a decoder circuit for matching each input pattern with an address, and memories (SRAM cells) for storing a value in the register of each address. FIG. 57C shows an example of the LUT circuit that can achieve symmetric Boolean functions.
A SRAM is a volatile memory, and loses stored information when the power supply is cut off. Therefore, so as to maintain data, a non-volatile memory (a flash memory, for example) is prepared externally, and the information stored in the non-volatile memory is loaded every time the power supply is resumed.
Recently, studies have been made on a circuit that has a neuron MOS (hereinafter referred to as the “νMOS ”) in the logic circuit blocks. This circuit has been developed as a reconfigurable logic circuit based on principles entirely different from those of the FPGA according to the LUT method (disclosed by T. Shibata and T. Ohmi in IEEE Trans. Electron Dev. ED-39 (1992) pp. 1444-1455 and IEEE Trans. Electron Dev. ED-40 (1993) pp. 570-576, and by Hiroshi Sawada, Kazuo Aoyama, Akira Nagoya, and Kazuo Nakajima in “Consideration for a Reconfigurable Logic Device using Neuron MOS Transistors”, IEICE Tech. Report, Vol. 99, No. 481, (1999) pp. 41-48). Using νMOS, symmetric functions can be efficiently realized. Although the functions are limited compared with the functions according to the LUT method, attention is being drawn to this method, as a large number of symmetric functions appear in the stage of logic design.
FIG. 56 illustrates an example structure of a logic circuit that can achieve symmetric Boolean functions. This logic circuit includes three pre-inverters 201, 203, and 205 that employ νMOS structures, and a main inverter 207 that also employs the νMOS structure. In the pre-inverters that serve as input units, digital values are input via equal capacitances. The inverters 201, 203, 205, and 207 have different logic threshold values from one another. In the drawing, Vk/n indicates that the number of inputs to the inverter is n, and the logic threshold value is Vk/n with respect to the logic level “1”.
Also, inputs are denoted by A and B, and the input of each control signal is denoted by Ck (k=0, 1, 2). The input to the main inverter 207 is controlled with Ck, thereby achieving a desired symmetric function. In the operation of this circuit, if Ck is “1”, the output is “0” only when the number of “1”s in the input is k. In other cases, the output is “1”. For example, if C0 and C2 are “1” and C1 is “0”, the output is “0” when the number of “1”s is 0 (A=B=“0”) and when the number of “1”s is 2 (A=B=“1”), but the output is “1” when the number of “1”s is 1 (A or B=“1”). Thus, a XOR logic circuit is obtained.